The present invention generally relates to spread spectrum communication, and more particularly, to spread spectrum transmitters and processing methods that provide for degradation of spread spectrum feature detectors and that achieves a low probability of detection.
The state of the art used in intercept receivers switches, or periodically changes, the frequency of the carrier and or the frequency of the chip rate clock to limit the coherent integration. The state of the art is reflected in the book entitled "Spread Spectrum Signal Design AJ/LPE" by David Nicholson, Computer Science Press, 1988 (See Section 4.5, starting at page 179). Implementation of conventional intercept receivers is accomplished in one or two ways: (1) multiple chip matched filters with variable sampling rate to implement the multiple chip rate frequency, and tuneable oscillators to implement multiple carrier frequencies, or (2) a very high sampling rate with firmware-controlled digital chip matched filtering to implement switchable chip rate frequency, and tuneable oscillators to implement the switching carrier frequency. Direct sequence spread spectrum signals are intercepted and identified using an intercept receiver by recovering a spectral line corresponding to their carrier frequency or to their direct pseudo-noise chip rate.
It is an objective of the present invention to provide a spread spectrum transmitter that limits spread spectrum waveform detectability by such intercept receivers and thus provides for a low probability of detection utilizing only phase jitter of a single chip rate and/or a single carrier.